1. Field of Invention
The present invention relates to a dielectric layer and a method of fabricating the same; more particularly, the present invention relates to an ultra low dielectric constant (K) dielectric layer and a method of fabricating the same.
2. Description of Related Art
Due to the accelerated development of the integrated circuit (IC) process, the backend metal interconnect process and low dielectric constant (k) material process become increasingly significant. As IC process progresses to the deep submicron territory, the RC delay of metal interconnect seriously affects the operating speed of a device. Mitigating RC delay may be accomplished by using a low dielectric constant (k) material for the insulation layer of the multi-layer metal interconnect to reduce parasitic capacitance between metal layers.
A porous low-k dielectric layer is a dielectric material containing numerous voids therein. Since the dielectric constant of the air inside the voids is close to 1, the overall dielectric constant of the dielectric layer is greatly reduced to below about 2.5. This type of material is an ultra low k dielectric material.
Although the porous dielectric thin film provides a low k value, the porous characteristic may increase the complexity in integrating the copper conductive line process. First of all, the porous structure weakens the mechanical strength of a thin film, and the shear stress resulted from a chemical mechanical polishing process poses a challenge to the inherent weakness of the porous dielectric thin film. As shown in FIG. 6, the application of a porous low dielectric constant (k) dielectric layer in a semiconductor process is typically implemented by forming a dielectric barrier layer 602 on a substrate 600 before forming the porous low-k dielectric layer 604. After the formation of the porous low k dielectric layer 604, a silicon oxide cap layer 606 is formed covering the porous low k dielectric layer 604. A deposition process in forming the porous low k dielectric layer is commonly performed under a single temperature and a single pressure. However, the adhesion property at the interface between the porous low k dielectric layer 604 formed according to the conventional deposition process and the dielectric barrier layer 602 or the cap layer 606 is undesirable. The adhesion strength is normally smaller than 5 joules/cm2. In the subsequent etching process, lateral etching is generated at the interface between the porous low k dielectric layer and the dielectric barrier layer or the interface between the porous low k dielectric layer and the silicon oxide cap layer (as depicted by the D, C regions in the Figure) due to insufficient mechanical strength and differences in the etching selectivity. Hence, kink profile issue is resulted to adversely affect the step coverage of the metal dielectric barrier deposited in the dual damascene opening. Ultimately, voids are formed and the electrical performance and reliability of the metallization process are compromised.